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CPU Inference on AMD EPYC 9334: Real Numbers for LLM and TTS Workloads

By Codcompass TeamΒ·Β·4 min read

Current Situation Analysis

Training is a capital expenditure; inference is an operational tax. Once models enter production, compute costs scale linearly with traffic, and for many organizations, inference spend eclipses training budgets within months. The traditional hardware paradigm defaults to GPU clusters for all inference workloads, but this approach frequently misaligns with the actual performance characteristics of deployed models.

Training workloads are heavily compute-bound and thrive on high-bandwidth interconnects (NVLink/InfiniBand) across large GPU clusters. Inference, however, splits into two distinct phases with divergent bottlenecks:

  • Prefill: Compute-bound. The model processes input tokens, builds the KV cache, and generates the first output token.
  • Decode: Memory-bandwidth-bound. The model generates subsequent tokens sequentially by reading from the KV cache.

When serving quantized models (Q4/Q5), the decode phase becomes strictly limited by DRAM bandwidth rather than raw FLOPS. Defaulting to GPUs for these workloads often results in underutilized tensor cores, inflated TCO, and unnecessary latency from PCIe/NVLink data movement. Without proper workload routing, quantization alignment, and memory topology awareness, teams waste budget on hardware that doesn't match the bottleneck profile of their actual traffic.

WOW Moment: Key Findings

ApproachTTFT (s)Decode Throughput (tok/s)Memory Footprint (GB)RTF
CPU (EPYC 9334) + DeepSeek-R1-8B Q4_K_M4.127.8~6.2N/A
CPU (EPYC 9334) + DeepSeek-R1-8B FP168.18.1~16.0N/A
CPU (EPYC 9334) + GPT-OSS-20B Q43.618.3~11.5N/A
CPU (EPYC 9334) + GPT-OSS-20B FP163.626.2~22.0N/A
GPU (Nvidia L4) + DeepSeek-R1-8B FP16~2.116.7~14.0N/A
GPU (Nvidia L4) + GPT-OSS-20B FP16~1.85

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