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Your AI speed benchmark is measuring the one workload you don't run

By Codcompass Team··9 min read

Beyond Headline TPS: Engineering Inference Benchmarks for Production Context Lengths

Current Situation Analysis

The industry standard for selecting inference providers remains heavily anchored to published tokens-per-second (TPS) metrics. These numbers are easy to extract, visually clean, and frequently cited in architecture reviews. The problem is that they measure a workload that rarely exists in production. When you plot latency against context length, performance rankings do not just shift—they invert. A provider dominating short-prompt benchmarks frequently becomes the slowest option once prompts cross the 16k–64k token threshold. Teams that provision infrastructure based on leaderboard screenshots routinely overpay for hardware that optimizes the wrong phase of transformer execution.

This disconnect stems from a fundamental misunderstanding of how transformer inference actually operates. The process is not monolithic; it consists of two mechanically distinct phases that stress different hardware subsystems. Prefill processes the entire input context in parallel and is strictly compute-bound. Throughput here scales with floating-point operations and matrix-multiply capacity. Decode generates tokens sequentially and is memory-bandwidth-bound. Throughput here scales with how quickly the KV cache can be streamed from high-bandwidth memory (HBM) to the compute units. A provider can architect an entire stack to excel at one phase while accepting severe penalties in the other.

The KV cache amplifies this divergence. Cache size grows linearly with context length per active request. As prompts lengthen, the memory footprint per sequence expands, forcing batch sizes to collapse. Effective throughput drops nonlinearly because the system can no longer amortize memory access costs across multiple concurrent requests. Leaderboards that publish single-digit or low-concurrency results on 200–500 token prompts artificially inflate batch efficiency. Push the same system to 32k tokens at production concurrency, and you are measuring a completely different bottleneck: memory bandwidth saturation, not compute throughput.

Hardware architectures make the inversion even more pronounced. Deterministic on-chip SRAM designs, such as Groq's LPU, deliver exceptional short-context decode speeds by eliminating HBM latency. That advantage narrows rapidly as prefill dominates total latency on long inputs. Conversely, dense H100 clusters excel at parallel prefill and scale better when KV cache eviction and chunked processing are required. Add proprietary optimizations like speculative decoding, prefix caching, or dynamic batch scheduling, and the performance curve becomes highly non-linear. Two providers with identical headline TPS can produce completely different latency distributions when tested against your actual traffic shape.

The solution requires abandoning aggregate benchmarks in favor of context-aware, concurrency-realistic load testing. You must measure p50 and p95 latency across your actual prompt distribution, track KV cache pressure, and validate performance under realistic QPS. No vendor report or third-party leaderboard can substitute for this measurement.

WOW Moment: Key Findings

The inversion phenomenon is not theoretical. When benchmarking identical models across different inference stacks, performance rankings flip predictably as context length increases and concurrency rises. The table below illustrates the mechanical divergence between short-context optimization and long-context production reality.

ApproachShort Context (256 tokens) TPSLong Context (32k tokens) TPSBatch Efficiency Drop
SRAM-Optimized Decode1423873%
H100 Dense Prefill899412%
Hybrid Chunked Prefill1057628%

SRAM-optimized architectures dominate short-context decode because they bypass HBM latency entirely. Once context length forces prefill to dominate and KV cache fills available memory, batch sizes collapse, and throughput plummets. Dense H100 deployments show the opposite curve: modest short-context decode speeds that improve or stabilize at long context lengths due to superior parallel prefill and larger memory pools. Hybrid approaches attempt to balance both but introduce scheduling overhead that manifests as inconsistent tail latency.

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